1. Field of the Invention
The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly to a method for forming a contact hole which can prevent an isolation region from being damaged because there is little overlap margin for a contact hole in the active region, when a contact hole is formed over both an active region and an isolation region, i.e., when a borderless contact hole is formed.
2. Description of the Prior Art
According to the design of the structure of a logic device, it is necessary to form a contact hole on a gate or active region only. However, as the dimensions of a logic device are reduced, an overlap margin for a contact hole gradually decreases in the active region. As a result, due to a misalignment phenomena caused from a lithography process, a contact hole, which is meant to be formed only in an active region, may be sometimes be partially formed in an isolation region beyond the border of the active region. Such a contact hole is called as xe2x80x9cborderless contact hole.xe2x80x9d
In the conventional process of manufacturing semiconductor devices, it is common to form a contact hole by performing dry etching using plasma formed by activating a xe2x80x98CxFy+O2xe2x80x99 gas, wherein the xe2x80x98CxFyxe2x80x99 means a gas selected from a group consisting of CF4, C2F6, C4F8, C5F8, etc., or a combination thereof. If desired, CHF3, Ar or the like may be added to that gas or the combination.
Polysilicon or silicide employed for forming a gate or active region has a characteristic of being scarcely etched by such plasma. In such a case, no damage is caused while a contact hole is being etched. However, a silicon oxide-based material (SiO2-xcex2) employed for forming an isolation region has a characteristic of being easily etched by such plasma. Therefore, a problem arises in that an isolation region is deeply and sharply hollowed out in the process of forming a borderless hole.
FIG. 1 is a drawing for illustrating the problematic situation when a contact hole is formed without using an etch-stop layer. In the drawing, 1 designates a silicon substrate, 2 designates a shallow trench isolation (STI), 3 designates a well, 4 designates a gate oxide layer, 5 designates a gate (polysilicon), 6 designates a silicide layer, 7 designates a spacer, 8 designates a source, 9 designates a drain, 10 designates an interlayer insulation layer, and 11 designates a contact hole.
As the dimensions of logic devices are reduced, the overlap margin for a contact hole decreases in the active region. If such an overlap margin for a contact hole is insufficient in an active region, the contact hole, which is meant to be formed only in the active region, is formed into an isolation region, beyond the border of the active region. As a result, a problem is caused in that the isolation region is deeply and sharply hollowed out, as shown in the drawing. If the isolation region is damaged in the process of forming a contact hole like this, leakage current or deterioration of the properties is caused in a resulting semiconductor device, thereby causing problems in operation of the device.
Therefore, in order to solve this problem, a contact hole is formed using an etch-stop layer in a conventional semiconductor device manufacturing process, which will now be sequentially described with reference to FIG. 2.
Referring to FIG. 2a, a predetermined thickness of a pad oxide layer (SiO2) 22 is deposited on a silicon substrate 21, and then a predetermined thickness of a silicon nitride layer (Si3N4) 23 is deposited on the pad oxide layer 22. Herein, the deposited silicon nitride layer 23 is used as a polish-stop layer when an oxidation material formed in a subsequent step for filling a trench is planarized using chemical mechanical polishing (CMP) process.
The pad oxide layer 22 serves as a buffer layer for alleviating the mechanical stress influencing on the silicon substrate 21; stress which are induced by the silicon nitride layer 23 having been deposited on the pad oxide layer 22. The thickness of the pad oxide layer 22 and the thickness of the silicon nitride layer 23 may be varied depending on the type of process employed, wherein the pad oxide layer 22 is applied to a thickness of about 70 xc3x85 to 200 xc3x85 and the silicon nitride layer 23 is applied to a thickness of about 500 xc3x85 to 1500 xc3x85.
Next, after a photoresist layer 24 is coated on the silicon nitride layer 23, a pattern of STI (shallow trench isolation) is formed by exposing and developing the photoresist layer 24.
Then, the silicon nitride layer 23 and the pad oxide layer 22 are completely etched by dry etching using activated plasma. Activated gases of plasma may be varied depending on the type of employed process. In general, however, a gas formed by mixing CxFy, HoHpFq, Ar, etc., in a predetermined ratio is mainly used for generating plasma. If the dry etching is continuously performed using activated plasma, a trench 25 is formed in the silicon substrate 21. When forming the trench 25 in the silicon substrate 21, plasma is generated mainly using a gas formed by properly mixing Cl2, HBr, N2, Ar, etc. After the silicon substrate 21 is etched to a desired depth, the remaining photoresist is completely removed.
Thereafter, the trench 25 formed in the step shown in FIG. 2c is filled with an oxide layer (SiO2) 26 deposited using a plasma enhanced chemical vapor deposition (PECVD) process. Here, one or more stepped portions may be formed in the top surface of the deposited oxide layer, which reflects the surface topology of a layer laid under the oxide layer.
The top surface of the oxide layer 26 deposited in the step of FIG. 2a is planarized and the oxide layer 26 deposited on the silicon nitride layer 23xe2x80x2 is removed, using CMP process, as shown in FIG. 2b. At this time, the silicon nitride layer 23xe2x80x2 serves as a polish-stop layer to prevent the silicon substrate 21 from being polished. During this step, the silicon nitride layer 23xe2x80x2 is partially polished and thus its thickness is reduced.
Referring to FIG. 2c, the remaining silicon nitride 23xe2x80x2 is removed using a phosphoric acid aqueous solution (H3PO4). If the concentration and temperature of the phosphoric acid aqueous solution of are properly controlled, the etch selectivity ratio of a typical SiO2 layer to the silicon nitride 23xe2x80x2 can be made to exceed about 1:50. Therefore, using the phosphoric acid aqueous solution, it is possible to completely remove the remaining silicon nitride film 23xe2x80x2 without damaging the oxide layer 26 filled in the trench 25.
Referring to FIG. 2d, a well 27, a gate 28, a spacer 29, a source/drain 30, and a silicide layer 31 are formed in accordance with the method of manufacturing a typical logic device.
Next, a silicon nitride (Si3N4) layer 32 is thinly deposited on the entire surface to a thickness of about 200 xc3x85 to 400 xc3x85. The deposited silicon nitride layer 32 serves as an etch-stop layer in a subsequent step for forming a contact hole.
Referring to FIG. 2e, after an interlayer oxide film 33 is deposited, the top surface of the interlayer oxide film 33 is planarized using chemical mechanical polishing process. In general, the interlayer oxide film 33 has a thickness of about 7,000 xc3x85 to 9,000 xc3x85 after the planarization is completed. In most cases, even if the thickness of the interlayer oxide film 33 is controlled to be constant and its planarization is completed, some variations in thickness exist in the interlayer oxide film, due to incompleteness of deposition and subsequent polishing steps.
Next, a photoresist layer 34 is coated on the interlayer oxide film 33, exposed and developed to pattern a form of contact hole.
Referring to FIG. 2f, the interlayer oxide film 33 is etched using plasma generated by activating a xe2x80x98CxFy+O2xe2x80x99 gas as a main component, so that a contact hole is formed within the interlayer oxide film 33. The etching proceeds in the following manner. The etching is performed using plasma generated by activating a gas having a relatively high ratio of C TO F, for example, C4F8 or C5F8 gas, with a minimum amount of O2 being added. If the etching proceeds in this manner, the interlayer oxide film 33 is relatively well etched but an etch-stop phenomenon is generated in the silicon nitride layer 32.
Therefore, even if variations in thickness had been caused in the interlayer oxide film 33 according to the various parts of the wafer in the abovementioned process, those variations are completely removed if the etching reaches the silicon nitride layer 32. If the etching of the interlayer oxide film 33 is completed, the plasma activation condition is changed so that the silicon nitride layer 32 can be etched well. That is, the etching proceeds using plasma generated by activating a gas having a reduced ratio of C to F with an increased amount of O2.
Herein, because the silicon nitride layer deposited in the aforementioned process is thin, it is not necessary to perform excessive over-etching in the silicon nitride layer (for example, for 30% over-etch, it is necessary to perform over-etch of 2,100 to 2,700 xc3x85 if no etch-stop layer exists, whereas it is sufficient to perform over-etching of 60 to 120 xc3x85 if an etch-stop layer is exist). Accordingly, even if a part of a contact hole, which is meant to be formed within an active region, is partially formed in the isolation region due to misalignment resulting from a lithography process, the problem of the isolation region being deeply and sharply hollowed out will not arise.
When a contact hole is formed according to the aforementioned process, an isolation region is not deeply and sharply hollowed out, as shown in FIG. 2k, even if a part of the contact hole is formed in the isolation region. However, the aforementioned process includes some problems, as follows.
(1) In general, a deposited silicon layer induces a strong compressive stress of about 109dynes/cm2. Such strong stress induced by a silicon nitride layer deposited on an active region may deform the crystal structure of the active region, thereby resulting in deterioration of characteristics of a resulting semiconductor device.
(2) In order to properly deposit a silicon nitride layer, an environment of high temperature in the range of about 700 to 1,000 xc2x0 C. is required. However, such a high temperature environment may change the operating characteristics of a transistor which has been optimized prior to depositing the silicon nitride layer.
(3) According to an existing method for manufacturing a logic device, silicide (a compound of silicon and a metallic component, i.e., Ti or Co) is formed prior to deposition of a silicon nitride layer. However, the high temperature environment in the range of about 700 to 1,000 xc2x0 C. required for deposition of a silicon nitride layer may cause deterioration of the characteristics of previously formed silicide.
(4) In the aforementioned process, a silicon nitride layer is deposited on both of an active region and an isolation region. The silicon nitride layer deposited on the isolation region is helpful in that it serves as an etch-stop layer. If no etch-stop layer exists, however, the active region will be lost when forming a contact hole, thereby causing junction leakage in a resulting semiconductor device.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a method for forming a contact hole in a semiconductor device, which can prevent an isolation region from being damaged because there is little overlap margin for the contact hole in the active region, when a contact hole is formed in both an active region and an isolation region, i.e., when a borderless contact hole is formed.
It is also an object of the present invention to provide a method for forming a contact hole in a semiconductor device, wherein a nitride layer is formed beforehand on an active region to solve the problem that characteristics of the device are caused to deteriorate due to the deformation of the lattice structure of the silicon surface in the active region, the deformation resulting from ion implantation.
It is another object of the present invention to provide a method for forming a contact hole in a semiconductor device, wherein a nitride layer is formed beforehand on an active region, thereby simplifying the entire process.
It is still another object of the present invention to provide a method for forming a contact hole in a semiconductor device, wherein a nitride layer formed beforehand serves as an etch-stop layer in the step of etching a borderless contact hole, thereby being capable of securing a process margin.
In order to accomplish the above objects, according to the present invention, there is provided a method for forming a contact hole in a semiconductor device comprising the steps of:
forming a pad oxide layer and a first silicon nitride layer to a predetermined thickness on a silicon substrate;
forming a trench for shallow trench isolation by dry etching the first silicon nitride layer, the pad oxide layer and the silicon substrate;
depositing an oxide layer on the entire structure formed through the above steps, using a plasma enhanced chemical vapor deposition (PECVD) process, so that the trench is sufficiently filled with the oxide layer;
planarizing the oxide layer by means of chemical mechanical polishing process, so that the top of the first silicon nitride layer is exposed;
recessing a part of the oxide layer filled in the trench by means of first plasma etching;
forming a second silicon nitride over the entire structure formed in the above steps to a thickness thicker than the recessed depth of the oxide layer;
planarizing the second silicon nitride layer using CMP process, so that the top of the first silicon nitride is exposed and partially planarized;
selectively removing the first silicon nitride layer and the pad oxide layer by means of a second plasma etching in the portions where a gate and a space are to be formed;
forming a well, a gate, a spacer and a source/drain, and then forming a silicide layer;
depositing an interlayer oxide film on the above structure, and then planarizing the top of the interlayer oxide film using CMP process;
coating a photoresist layer on the interlayer oxide film and then forming a shape of a contact hole by exposing and developing the photoresist layer; and
forming a contact hole in the interlayer oxide layer by removing a part of the interlayer oxide layer using a third plasma etching.